Modern x86 processors invest a lot of time in rearranging instructions, shadowing registers, and the like, with the intent to parallelize instructions without having to reveal this fact to the end user.

Itanium code takes the form of fixed-width chunks, but they're a lot longer than a RISC instruction and contain multiple small instructions. All of these run in parallel. It's illegal to have any conflicts within a chunk (such as two instructions writing to the same register, or one writing from a register that another one is reading).

Itanium exposes this parallelism to compiler authors, so that a sufficiently smart code generator can take advantage of this. In practice, the sufficiently smart compilers never materialized.

An interesting innovation which only was used in the IA-64 simulators apparently, was the neural branch predictor: https://en.wikipedia.org/wiki/Branch_predictor#Neural_branch...

VLIW architecture with predicated execution.

I don't think predicated execution is unheard of, ARM has the same concept (although it's limited to flags instead of what seems like one-bit registers). The feature has since been dropped in AArch64 though.