It doesn't really say that it needs to use 3x more area, but that 3x more gets consumed due to "advanced packaging and manfuacturing complexity". Which doesn't properly explain why it consumes 3x more and could simply mean they have a bad yield and 2/3 produced is garbage.
You make HBM by stacking a whole bunch of dies on top of each other. The signals from the upper dies need to pass through vias in the lower dies to get out - taking up valuable die space in a way which simply isn't needed with regular DDR. Similarly, HBM has a far wider bus, so each individual die has, say, 16 banks of depth 32, rather than 4 banks of depth 128. That's more control area needed per byte of memory.
Those two combined already result in a huge reduction in bytes per mm2, so with the same wafer processing capacity you're producing far less byte of memory. Add to that a complicated chain of HBM-specific packaging steps, and you're now also losing a decent bunch of perfectly-fine dies because rather than putting it into DDR you tried making a HBM sandwich and screwed up.
Even if the memory cells are the same and have an absolutely identical yield, HBM will always end up having a significantly lower output. That's just the cost of stacking, but some people are willing to pay the per-gigabyte price penalty in return for the higher bandwidth.
This might not be far off the mark. You are irreversibly linking the fates of these devices after a certain stage of manufacturing. If something goes wrong at final packaging time, you lose all dies instead of one.
Classic DRAM stacks up to four wafers on top of each other and then is packaged with BGAs. The manufacturer can check the DRAM chips independently.
Soldering the DRAM onto a PCB is such a reliable process that there is almost zero risk of defects and even if a defect occurs the damage is limited. If the DRAM is soldered onto a DIMM the risk of a defect on the non memory hardware is non-existent. If the DRAM is soldered straight onto an SBC or GPU, then the DRAM can be removed to save the precious SoC or GPU chips.
Meanwhile HBM is the ultimate nightmare scenario. You stack up to 16 DRAM wafers on top of each other. One defect and the whole stack is worthless and that was actually the easy part.
In stage two things get even worse. You now have your accelerator chip and you must place the HBM on that chip. E.g. Blackwell GB300 has eight HBM stacks and the accelerator chip has a bigger area than the HBM. You must get the packaging right eight times in a row or you have wasted not only the DRAM silicon, but also the accelerator silicon because HBM cannot be removed and defects are permanent.
The issue here isn't just the yield of the HBM (which is obviously lower if you have taller stacks) but rather the yield of the combined HBM-based product, which is why doesn't make sense to say it needs more area but it is completely correct to say that HBM leads to more silicon being consumed. Hence it doesn't make sense to talk about yield of the HBM itself, because it is always part of an integrated product.
From what I understand the whole point is avoiding the need to stomp pedals or otherwise touch them during live performance.
Some pedals have a bunch of knobs which are a pain to adjust during live performance between the songs. So some pedals support changing the settings using MIDI interface. This device has builtin library of control codes fur such pedals. That way you can program presets for your MIDI controlled pedals in the storm summoner and during live performance quickly switch between presets with a click of single button as opposed to remember which of the half dozen pedals need to be stomped on/off for each song or worse adjusting the knobs.
Oh, ok thanks for the explanation, I can see the utility of it there. I thought it was more like "hey here's a stompbox but you can't stomp it and we switched those pesky knobs with a touch-senstive surface like cars did and everyone hates".
All without a DAW too I'm guessing? I use an FCB-1010 for a lot of things but yeah it's obviously pretty useless without a DAW.
People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores.
On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512.
On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting.
At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point.
So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.
If you'd limit yourself to cores implementing the Application profile of ARM (Armv8-A etc), you'd do the same and limit yourself to cores implementing the Application profile of RISC-V (RVA23 etc). In that case, you can assume vector instructions and everything else.
If you don't, you get the exact same kind of question with ARM as with RISC-V. Do you use NEON or with SVE? Or do you conservatively compile without vector instructions at all even though it could possibly result in speed-ups for some loops?
I don't think you're giving ARM credit for the ever growing pile of features which are always optional or optional only on some versions of the ISA.
For example, can you use FEAT_CSSC to improve code size and performance? Well, if the target is <v8.7, the answer is no. If it's v8.7 or v8.8, well, then it depends on whether your specific implementation has it. Only after v8.9 is it mandatory.
Targeting armv8a is the moral equivalent of targeting RV64GC insofar as it will run on any application class core. Targeting that, however, leaves a fair bit of useful ISA enhancements on the table, and so you tend not to want to do that if you can get away with it.
Micropython runs on tons of stuff and while it isnt capital-P Python, its close enough for doing a wide variety of embedded work without learning a new language/libraries/etc.
Matching decompilation is a verifiable target that ensures feature parity but it says nothing about being reasonable non slop decompilation.
Disassembler output can relatively easily match original binary, I doubt anyone would consider it decompilation.
Let's say you add requirement of being higher abstraction language than assembly. You can translate the assembly code 1:1 with simple string substitions to C code which would provably replicate the behavior of program perfectly. I would consider that more of hard coded emulation, opposite of JIT like ahead of time code translation. Just because the intermediate langauge is higher level language than assembly doesn't automatically mean that the program text operates at higher level of abstraction than assembly.
I have seen plenty of decompilation projects where you start reading the code many functions contain nonsensical variable reuse (and name that match the register names), address calculations and memory casts and array calculations, arrays of function pointers, offsets within structures which strongly mirrors the assembly code.
The problem is that you can't draw a hard line how good do the variable/function names need to be so that it can be considered decompilation instead of hard coded emulation. It's hard to draw a line for how much of higher level language features you need to use to be considered decompilation. It's hard to define how logical the control flow needs to be. The line becomes blurrier by system programmers approaching it from the other side. Sometimes an extensively optimized code can contain a lot more manual memory mangling, index and offset calculations, manual unrolling than the language requires. So many C programs with homebrew systems of emulating virtual functions using structs of pointers. In such situations it's hard to tell if decompilation is incomplete or whether program was written that way from start.
Another possibility of junk decompilation (which perfectly compiles to byte identical copy of original executable) is program which depends on exact program layout in memory or undefined aspects of programming language. It would perfectly replicate original behavior on original hardware/compiler, but provide 0 insights in intended program behavior and fail miserably when attempting to modify the code or port it to different hardware/compiler. For example the "decompiled" code might intentionally peform out of bounds array access thus touching completely different variable or depend on fallthrough between functions lacking return statement.
Taking it to the extreme would be something like:
```
char data[] = {0x10, 0x12, 0xab, 0xcf, ...}; // bytes corresponding to majority of original program.
int main(){
((void*())data)(); // cast the array to function pointer and execute it
}
```
It might behave exactly like original program, but that's junk decompilation.
You could add additional restriction that C program isn't allowed to exploit any undefined or machine specific behavior, but then there is very high chance that even original program wouldn't satisfy it.
Original program might also contain parts of it written in assembly for performance reasons or because that was only way to access certain hardware features. What does it mean for decompilation? Is decompiled code not allowed to use the same techniques. If decompiled code is allowed to have some pieces of assembly what stops it from using it for everything. There is no way of knowing precisely how much assembly the original program used.
There are two bad properties in terms of interactivity (and for other uses).
In some configurations hyperbezier explodes towards infinity or at least way outside the bounds of control points. Cubic beziers don't do that, if control points are bounded the curve will be as well. This is direct result of how cubic bezier can be calculated with series of linear interpolations.
Other issue was that there were discontinuities while moving through parameter space or at least very sudden jumps, small changes of control points caused curve flip to completely different shape.
Even if you ignore the nonavoidable copies which happen during normal usage of digital files there is no way they don't dozens of different real copies of their training dataset across many different servers accessible by many people.
It's a blog of a niche computer peripheral company not a store listing. And it's not their first product either, only blog is having problems rest of website is still wotking and in the store you can get a pretty good picture of what their typical kits look like. Most likely only sensor, the only through hole component needs soldering. They also ofer fully assembled versions, although initial preorer batch might be kits only .
All LEDs are like this. It's horrible. The only good thing about it is that every professional in the entire industry has come to expect that if it's an LED, something somewhere will be wrong with it.
By all LEDs do you mean addressable and other multipin LEDs? Never seen anything weird with classic 5mm/3mm. The flat side+leg length is quite reliable. 0805/1206 smd LEDs also seem mostly fine.
The cathode marks are basically randomly assigned. This is because each company more or less designs one leadframe/package structure per size or type of LED. Sounds reasonable, right? But LED dice aren't made of silicon. They're made of weirdo high-bandgap materials, and every color is different in its own way. From physics alone, some of the colors end up with cathodes on top of the dice and some of the colors end up with anodes on top. They all get bonded in to the package the same way. So... that marking built in to the package? That's always the "top of die" wire next to it. But "top of die" might be cathode, or it might be anode. Flip a freaking coin!
If you want to see this clearly, find a datasheet that covers an entire series of LEDs. Vishay often does this, here's one: https://www.vishay.com/docs/82437/vlmo1300.pdf . They'll tell you the marking locations for each color individually. Notice how they're all completely different? Yeah.
Could the manufacturers do better? Yes. Yes, they could. We all wish they would do better. But they do not. So LEDs are the stuff of nightmares for people who assemble boards.
Through-hole parts are somewhat better (but there are certainly rogues!), but this is 2026: the volume's in surface mount.
Multipin LEDs are no better. The SMD no-lead versions are again fairly randomly marked. The PLCC-4 types are usually "cutoff corner near pin 1", but I've seen it as pin 4... or pin 2... constant vigilance is the only solution. Constant vigilance!
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